As the electronic instruments recently exhibit higher functions and have lighter weights and smaller sizes, electronic members are integrated with a higher density and mounted in the instruments with a higher density. Semiconductor packages become smaller and have a greater number of pins.
As the conventional circuit substrates which are called printed wiring boards, wiring substrates prepared as described in the following are mainly used. A copper foil attached to a glass epoxy board which is a laminate obtained by impregnating a woven fabric of a glass fiber with an epoxy resin is patterned; a plurality of such laminates are laminated; holes penetrating the obtained laminate are formed by a drill and vias are formed by plating the wall surface of the holes; and layers are electrically connected with each other through the vias. However, since parts mounted to the wiring substrates become smaller and are placed more densely, problems arise on the mounting on the above wiring substrates due to insufficient density of the wiring.
Under the above circumstances, built-up multi-layer wiring boards are used recently. The built-up multi-layer wiring is formed by laminating a plurality of insulation layers constituted with a resin alone and a plurality of layers of a conductor. As the process for forming a via, various processes such as the laser process, the plasma process and the photo process are used in place of the drilling which has heretofore been used. Vias having a small diameter are arranged and a great density can be achieved. As the portion for connecting layers, a blind via and a buried via (a via filled with a conductive material) are used. The buried via is attracting attention since a stacked via in which a via is formed on top of another via can be formed. The process for forming the buried via includes a process of filling the via hole by plating and a process of filling the via hole with a conductive paste.
In Japanese Patent Application Laid-Open No. Heisei 11(1999)-204939, a multi-layer circuit substrate is disclosed. The multi-layer circuit substrate has a construction such that an insulation sheet has a wiring pattern disposed at least on one face and conductive via holes which penetrate the insulation sheet from the front face to the back face, a circuit substrate has electrodes for connection which are disposed at desired positions on the front face and the back face and electrically connected with the via hole, and a plurality of the insulation sheets and a plurality of the circuit substrates are alternately laminated. The insulation layer is constituted with a cured layer of a thermosetting adhesive which has a viscosity decreasing to 100 Pa·s or smaller by heating at a temperature in the range of 100 to 300° C. and is cured to at least 70 to 80% by being left standing at a temperature in the above range. The density of the portion for connecting layers can be increased by using the above multi-layer circuit substrate. For forming the electrode for connection, it is attempted that electric connection is formed by using a conductive adhesive or an alloy containing Sn as the main component such as Sn—Pb solder at a temperature of 300° C. or lower. It is also attempted that Au and Sn is formed on the surface of the electrode for connection and electrical connection is formed with an Au—Sn alloy. However, the conductive adhesive has a problem in that reliability of the connection is poor and the connection with the alloy containing Sn as the main component has a problem in that the wetting between the metals is poor since the surface of Sn is not cleaned and the connection is not sufficiently formed.
In Japanese Patent Application Laid-Open No. Heisei 8(1996)-195560, as the process for producing a circuit substrate which can be used for decreasing the size and the thickness of the substrate and for decreasing the area of the portion for electric connection of the conductor layer, a process for producing a printed circuit substrate which comprises molding under a pressure laminates formed by stacking a prescribed number of layers of an insulating material having a layer of a conductor circuit on one or both faces and layers of an insulating material having no layers of a conductor circuit and, at the same time, electrically connecting at least prescribed two stacked layers of a conductor circuit with each other, is described. In the above process, the layers of an insulating material are all formed as layers of an insulating material having a sheet form and not containing glass fiber, a protrusion (a block of a metal) composed of a conductor for electrically connecting layers of a conductor circuit is disposed at a prescribed position on the layer of a conductor circuit, and the protrusion breaks and penetrates the resin layer of an insulating material by the force of pressing the laminate using a press jig plate so that the protrusion is brought into contact with and attached to the faced circuit layer of a conductive material under a pressure. It is also described that, in the above process, a solder layer having a melting point higher than the temperature of curing the resin in the resin layer for insulation is disposed at the tip of the protrusion, the solder layer is brought into contact with the layer of a conductor circuit by breaking and penetrating the resin layer for insulation by pressing under heating, the solder layer is thereafter melted by elevating the temperature to the melting point of the solder in this condition so that the protrusion is connected with the layer of a conductor circuit, and the solder layer is then cooled and solidified. In accordance with this process, a stacked via in which a via is formed on top of another via can be formed and the density of the portion for connecting layers can be increased since the connection of the layers is conducted through the protrusion (a block of a metal) composed of the conductor. However, in the former process, the electrical connection is made through the physical contact alone and reliability is considered to be poor. In the latter process, the solder cannot spread by wetting and the soldering becomes impossible unless the surface of the solder layer at the tip of the protrusion and the surface of the layer of a conductor circuit are sufficiently cleaned.
The present inventors have heretofore examined the process for connecting layers in a multi-layer wiring board and proposed a process in which a conductor post is formed on any of lands disposed in a wiring pattern having a land for connecting layers and in a member to be connected having a land for connecting layers for connection with the wiring pattern, a solder layer is formed at least on the surface of the conductor post or on the land faced to the conductor post, the conductor post and the land faced to the conductor post are tightly attached and pressed together via an adhesive layer, and then the attached portions are heated at the melting point of the solder to achieve the connection between layers. However, when the solder is pressed before the solder is melted, the solder is deformed by the contact with the metal land for connecting layers and the tip is flattened. In this condition, a thin adhesive layer is present between the layers. Although the adhesive layer has the function of cleaning the surface necessary for soldering, the function of cleaning the surface is not sufficiently exhibited since the absolute amount of the adhesive layer is small. Therefore, a problem arises in that the excellent soldering is not achieved. In the portion of the solder layer which is not flattened, the function of cleaning the surface is sufficiently exhibited since the adhesive layer is sufficiently present in the vinicity. Therefore, excellent soldering can be exhibited between the solder and the land for connecting layers when the solder is melted. In other words, the soldering is achieved while the resin remains in some portions. This condition is not considered to provide an excellent soldered portion.
Therefore, in a multi-layer wiring board on which a semiconductor chip is mounted, it has been desired that a technology for surely achieving the connection of layers and producing a highly reliable multi-layer wiring board with excellent productivity is developed.
On the other hand, in the field of mounting a semiconductor chip, semiconductor devices using the flip chip connection have been attracting attention due to the excellent electric properties and are already produced in a great amount.
In the process of flip chip connection, heretofore, electrode terminals in a semiconductor chip and connecting pads of a substrate are first connected by using conductive bumps, a liquid resin is then cast into a gap between the semiconductor chip and the substrate (the underfill step), and the resin is cured by heating. However, in accordance with this process, the heating step is necessary for each of the connection of the terminals and the curing of the resin and the cost inevitably increases. Moreover, it takes time for casting the resin since the gap between the chip and the substrate is very narrow.
To overcome the above problems, various processes for the single-step connection in which the connection and the casting of the resin are conducted simultaneously have been studied. As one of such processes under the study, a process in which a chip or a substrate is coated with a resin containing a component for activating the surface of a metal, the chip is placed on the substrate, and the connection of the terminals and the underfill are simultaneously achieved by heating the resultant combination without further treatments, which is the so-called non-flow underfill process, has been studied. Since the step of connection and the step of casting the resin can be conducted in a single step by using the non-flow underfill process, the investment on apparatuses and the cost of operation can be decreased due to the remarkable simplification of the production steps. Moreover, the through put can be increased since the step of casting the resin into a narrow gap which takes a great time can be omitted. In this process, when the conductive bump is a solder bump, the solder bump is melted by heating and connected to another terminal or a pad. By continuing the heating in the same condition, the curing reaction of the resin proceeds and the entire face of the bonding can be fixed.
In the semiconductor device obtained by mounting a semiconductor flip chip to a wiring substrate in accordance with the non-flow underfill process, it is desired that technology for surely achieving the electric connection and producing a highly reliable semiconductor device with excellent productivity is developed similarly to the technology for the multi-layer wiring board.